| カテゴリ | 重要度 | ステータス | 解決状況 | 登録日時 | 最終更新 |
|---|---|---|---|---|---|
 ゲームプレイ | 中 | 解決済み | 修正済み | 2015-10-28 22:50 | 2015-10-29 20:57 |
| テスター | cuavas | 担当者 | cuavas | ソース | osborne/osborne1.cpp |
| バージョン | 0.166 | 発生バージョン | 修正バージョン | 0.168 | |
| 修正コミット | プルリク | ||||
| フラグ | |||||
| セット | osborne1 | ||||
| セット詳細 |
 osborne1 - Osborne-1 | ||||
| 概 要 | ROMバンキングが正しく動作していない。 | ||||
| 詳 細 | Osborne 1 can switch between ROM and memory mapped I/O or RAM in the low 16k of the address space. The logic to do this is rather convoluted, and involves several flipflops. From the schematic the following signals are significant in the selection of this bank: RESET* <= power-on reset generator NMI* <= reset key active low M1* <= (/M1 == 1) M1 <= (/M1 == 0) INTAK* <= (/IORQ == 0) && (/M1 == 0) && (/WR == 1) MREQ* <= (/MREQ == 1) || (/RFSH == 0) RD* <= (/RD == 1) ROM RD* <= (MREQ* == 1) || (RD* == 1) /NMI <= (NMI* == 1) || (UB6-5 == 1) UB6-5 (flipflop) write to 0x01 in I/O => 1 M1 0->1 => NMI* (i.e. set by writing to port 1 or the start of opcode fetch or interrupt acknowledge while reset key is not pressed, and cleared by start of opcode fetch or interrupt acknowledge while reset key is pressed) UB4-5 (flipflop) Write to 0x01 in I/O => 1 (INTAK* == 0) => 0 ((M1 == 1) || (ROM MODE* == 0)) 0->1 => UB6-5 ROM MODE* (flipflop) write to 0x01 in I/O => 1 (write to 0x00 in I/O) || (RESET* == 0) => 0 ((M1 == 1) || (ROM MODE* == 0)) 0->1 => UB4-5 ROM CE* <= (ROM MODE* == 1) || (ADDR15 == 1) || (ADDR14 == 1) || (ADDR15 == 1) IO REQ <= (ROM MODE* == 0) && (ADDR15 == 0) && (ADDR14 == 0) && (ADDR13 == 1) && (MREQ* == 0) I/O SEL* (flipflop) (I/O REQ == 0) => 1 CPU CLK 0->1 => (CHAR CLK* == 0) || (MEM CLK == 0) The ROM MODE* signal is the key one. Note the nasty feedback loops in the way flipflops are set. To handle banking properly, we need to track the UB6-5, UB4-5 an ROM MODE* flipflop values. The following signals need to be available: * I/O space writes (we get a nice callback for this already) * RESET* (power-on reset can be done in the device reset handler) * NMI* (comes from a currently unimplemented button, but simple enough) * /M1 output of Z80 CPU (not sure if this is available, need to detect edges) * /IORQ and /WR output of Z80 CPU (only used in conjunction with /M1 to detect interrupt acknowledge, level sensitive but we need the edge to trigger the transition) | ||||
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| 添付ファイル | |||||